The present invention relates to phase locked loops, and more particularly to an edge integrating phase detector for a phase lock loop that acts to minimize jitter due to noise of a timing system derived from an input signal while maintaining a relatively large bandwidth in the system to respond to timing variations in the input signal.
In a raster scanned video system a video waveform has a repetitive reference component, referred to as sync, that is used to generate timing for the system. To generate this timing it is necessary to lock a local oscillator to the sync component so that all processing within the system occurs at known timing relationships with the video waveform. Commonly a phase locked loop is used that compares the phase of a reference clock to a sync signal derived from the sync component and adjusts the frequency of the reference clock until the phase between the two signals has a predetermined value. Typically the video waveform is input to a sync stripper that provides the derived sync signal as a train of pulses, each pulse having a leading edge corresponding to a timing reference point on the video waveform. The sync stripper compares the video waveform with a fixed level, with the leading edges of the pulses in the derived sync signal occurring when the video waveform level crosses the fixed level in a given direction. Noise in the video waveform causes this crossing point to vary on a random basis, producing jitter in the derived sync signal.
The derived sync signal is input to a phase detector together with a clock signal derived from the video system clock. The difference in phase between the appropriate clock signal edge and the corresponding sync signal edge is converted into an error voltage that is applied to the system clock to adjust its frequency until the phase difference achieves the predetermined value. If there is noise on the video waveform that causes jitter in the derived sync signal, as described above the period between the pulses of the derived sync signal vary, and there is a constant correcting of the system clock such that the phase locked loop output has jitter relative to the input signal. To reduce this jitter effect due to noise, a loop filter having a very low bandwidth is inserted into the phase locked loop so that only an average variation in the period between pulses affects the timing of the phase locked loop. The low bandwidth loop filter, while effectively reducing jitter, reduces the response time to variations in the reference sync signal.
What is desired is a phase locked loop that reduces jitter due to noise on a video waveform while maintaining the ability to respond rapidly to variations in the video waveform.